1. Field
Various embodiments described herein relate to a computer-readable recording medium on which a verification support program for supporting verification of operation(s) of an arbitrary system is stored. The embodiments also relates to an information processor and to a verification support method.
2. Description of the Related Art
When a new system is developed and an application run by an OS (operating system) running on the system is developed, it has been heretofore necessary to evaluate the system itself and the application in terms of performance. In order to evaluate the performance of the application, the hardware environment of the system that runs the application must be taken into consideration. Accordingly, accurate evaluation of the performance cannot be made until the application is run on the system after completion of the development of the assumed system.
Accordingly, in recent years, a technique of making an evaluation of performance using a virtual machine has been offered as disclosed in Japanese Laid-open Patent Publication No. 8-241327. In particular, an application is run on the virtual machine that realizes a hardware environment for an assumed system by means of software without waiting for completion of development of the assumed system. FIG. 17 is a block diagram illustrating the configuration of a typical virtual machine. As shown in FIG. 17, the virtual machine (VM), 20, is realized by executing given software by means of an information processor 10.
The virtual machine 20 has a hardware model 21 that realizes hardware similar to the assumed system by means of software and a virtual machine (VM) monitor 22 for controlling the operation of the hardware devices (in the example of FIG. 17, a CPU, a hard macro, and a memory) implemented by the hardware model 21. The operation of an application 11 may be verified by activating an OS 13 on the virtual machine 20 and a driver 12 compliant with the hardware environment realized by the virtual machine 20.
FIG. 18 is a block diagram illustrating fundamental operations performed by the typical virtual machine. FIG. 18 depicts a procedure for the fundamental operations used when the application 11 is verified using the virtual machine 20. When the application 11 is read into the virtual machine 20, the CPU and hard macro inside the hardware model 21 are made to execute their respective given operations according to the descriptions of the application 11. The memory in the hardware model 21 is appropriately accessed according to the operations of the CPU and hard macro. Thus, data is written and read out.
More specifically, in the case of the CPU, instructions are first fetched from the application 11 (operation S11). The fetched instructions are executed (operation S12). According to the execution of the instructions, the register/memory is updated (operation S14). According to the update operation, a bus access is made (operation S13). When the update operation is completed, time and electric power that would be consumed if the same instructions were executed on a real machine are added (operations S15 and S16). Program control goes back to operation S11, where next instructions are fetched. With respect to the time and power consumption added in operations S15 and S16, values forecasted according to the performance of the real machine and actual measurement values are prepared in advance. These values are added.
Similarly, in the case of the hard macro, an algorithm according to the description of the application 11 is first implemented (operation S21). The register/memory is updated according to the implemented algorithm (operation S22). Then, according to the update process, a bus access is made (operation S23). When the update operation is completed, time and electric power that would be consumed if the same algorithm was implemented on a real machine are added also in this case (operations S24 and S25). Program control goes back to operation S21, where a next algorithm is implemented. With respect to the time and power consumption added in operations S24 and S25, values forecasted according to the performance of the real machine and actual measurement values are prepared in advance. These values are added.
The operations respectively performed by the CPU and hard macro are synchronized with each other under control of the virtual machine (VM) monitor 22. Accordingly, by acquiring the results of the execution of the operations performed by the virtual machine 20 and by obtaining the results of a simulation of cooperative processing between the CPU and hard macro in the same way as where the application 11 is run by the hardware model 21 similarly to when it is run by a real machine, the operations may be verified.
FIG. 19 is a block diagram illustrating verification support operations performed by an application using a typical virtual machine. As described previously, in order to realize a system assumed to support the verification performed by the application 11 using the virtual machine 20, it is essential that a C model creation module 30 refer to a hard macro specification 31 and that a C model 32 which is a simulation model of the hard macro be created.
The application 11 run by the virtual machine 20 cannot be employed unchanged in practice. Therefore, the application is converted into an app binary 42 by a compiler-assembler module 40. Also, it is necessary to create function map information 43 ancillary to the app binary 42. A simulation of the application 11 cannot be run by the virtual machine 20 until these preparations are completed.
The hard macro specification 31 employed to create the C model 32 is also exploited in manufacturing a real chip 60. In this case, an RTL (register transfer level) creation module 50 first creates an RTL statement from the hard macro specification 31. The real chip 60 is fabricated using the created RTL statement/net list 51, the net list being created from the RTL statement. The accuracy of the simulation may be checked by comparing the performance and power consumption obtained when the application 11 is implemented by the fabricated real chip 60 with forecasted performance and power consumption obtained by the simulation performed by the virtual machine 20.
However, in the case of a system under development in practice, there is a possibility that the specifications of the hardware environment are varied and hard macros are added frequently. Therefore, in many cases, it is difficult to prepare the correct hard macro specification 31. Even if the hard macro specification 31 may be prepared, a large amount of time and development cost are consumed to create the C model 32. In order to use the actually created C model 32, a verification work equivalent to designing of the real chip 60 is necessary. As a result, a heavy burden is imposed on the verifier. Consequently, there is the problem that this cannot be adopted as a realistic technique.
With respect to the application 11, the hardware environment for the actually operated system is not established. Therefore, the application often fails to operate normally on the virtual machine 20 if the app binary 42 is used unchanged. Accordingly, the app binary 42 must be modified so as to cope with the hardware environment of the virtual machine 20. There is the problem that as the system becomes more complex and needs more accurate verification, a longer time must be spent in performing a modification operation or actual verification operation.